1. Antoine,C.-Goff,B.L.: Timing Diagrams for Writing and Checking Logical and Behavioural Properties of Integrated Circuits. In. Proc.of Advanced Research Workshop on Correct Hardware Design Methodologies, Turin, June 1991.
2. Borriello,G.-Katz,R.H.: Synthesizing Transducers from Interface Specifications. In. Proc. of VLSI'87 (C.H.Sequin edt.), Elsevier Sc. Publisher, 1988, pp.403–418.
3. Cingel,V.: Specification and Verification of Timing in Digital Systems. Ph.D. Thesis, Department of Computer Science and Engineering, Slovak Technical University, Bratislava, Jan 1991, 175 pp (in Slovak).
4. Claesen,L. et al.: Efficient False Path Elimination Algorithm for Timing Verification by Event Graph Preprocessing. Integration, the VLSI journal, Vol.2, 1989, pp.173–188.
5. Dagenais,M.R.-Rumin,N.C.: Automatic Determination of Optimal Clocking Parameters in Synchronous MOS VLSI Circuits. In. Advanced in CAD for VLSI, Vol.5, 1987, pp.20–33.