On the optimisation of outside spacer bipolar transistors for 0.5 ?m high performance mixed analog/digital BiCMOS-Reference-Cited by-同舟云学术

On the optimisation of outside spacer bipolar transistors for 0.5 ?m high performance mixed analog/digital BiCMOS

Published:1996-10 Issue:5 Volume:79 Page:343-351
ISSN:0003-9039
Container-title:Electrical Engineering
language:en
Short-container-title:Electrical Engineering

Author:

Cuthbertson A.,Decoutere S.,Deferm L.

Publisher

Springer Science and Business Media LLC

Subject

General Engineering,Applied Mathematics,Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF01235875.pdf

Reference20 articles.

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2. Sone, K.; Yotsuyanagi, M.: Design Techniques for Analog BiCMOS Circuits. Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting, 80?86, 1994

3. El-Diwany, M.; McGregor, J.; Demirlioglu, E.; Huang, R.: 1.5 ?m Analog BiCMOS/DMOS Process for Medium Voltage and Current Power IC Applications of the 1995 Bipolar/BiCMOS Circuits and Technology Meeting, 142?145, 1995

4. Iranmanesh, A.; Ilderem, V.; Solheim, A.; Blair, C.; Lam, L.; Haas, F.; Leibiger, S.; Bouknight, L.; Lahri, R.; Biswal, M.; Bastani, B.: 0.6 ?m, Single Poly Advanced BiCMOS (ABiC IV) Technology for ASIC Applications. 1990 Symposium on VLSI Technology Digest Technical Papers, 87?88, 1990

5. Schutz, J.; Bohr, M.: A High Performance 0.35 ?m 3.3 V BiCMOS Technology Optimised for Product Porting from a 0.6 ?m 3.3 V BiCMOS Technology. Proceedings of the 1995 Bipolar/BiCMOS Circuits and Technology Meeting, 43?46, 1995