1. H.T. Kung, “Why Systolic Architectures?,”IEEE Computer, Vol. C-31, pp. 37–46, 1982.
2. H.T. Kung and C.E. Leiserson, “Systolic Arrays (for VLSI),” in I.S. Duff and G.W. Stewart (Eds.),Sparse Matrix Proceedings, 1978, pp. 256–282, SIAM 1979.
3. F.T. Leighton and C.E. Leiserson, “Wafer-Scale Integration of Systolic Arrays,”IEEE Trans. Computers, Vol. C-34, pp. 448–461, 1985.
4. D. Siewiorek and R. Swarz, “The Theory and Practice of Reliable System Design,” Bedford, MA: Digital Press, 1982.
5. S.R. Gupta and M.A. Bayoumi, “Concurrent Error Detection In Systolic Arrays For Real-Time DSP Applications,” R.W. Brodersen and H.S. Moscovitz (Eds.),VLSI Signal Processing III, New York: IEEE Press, 1988.