Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming-Reference-Cited by-同舟云学术

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Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming

Published:2005 Issue: Volume: Page:174-186
ISSN:0302-9743
Container-title:Automated Technology for Verification and Analysis
language:
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Author:

Li Tun,Guo Yang,Li SiKun,Liu GongJie

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/11562948_15.pdf

Reference23 articles.

1. Clarke, E., Grumberg, O., Peled, D.: Model Checking. MIT Press, Cambridge (1999)

2. Lecture Notes in Computer Science;S. Graf,1997

3. Detlefs, D., Nelson, G., Saxe, J.B.: Simplify: A theorem prover for program checking. Technical Report HPL-2003-148, HP Labs (2003)

4. Lecture Notes in Computer Science;T. Ball,2004

5. Ball, T., Rajamani, S.K.: Boolean programs: A model and process for software analysis. Technical Report 2000-14, Microsoft Research (February 2000)

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