1. T. Osabe, et al, “A Single-Electron Shut-Off Transistor for a Scalable Sub-0.1 um Memory”, (Hitachi) IEDM, December 2000, pp301.
2. K. Nakazato, et al, “PLED-Planar Localised Electron Devices”, (Hitachi/Cambridge Labs), IEDM, December 1997, pp 179.
3. H. Mizuta, et al, “Normally-off PLED (Planar Localised Electron Device) for non-volatile memory”, VLSI Technology Symposium, June 1998, pp128.
4. H. Ahmed, “Single Electron and Few Electron Memory Cells”, (Cambridge/Cavendish labs), IEDM, December, 1999, pp363.
5. K. Nakazato, et al, “Phase-state Low Electron-number Drive Random Access Memory (PLEDM)”, ISSCC, February 2000, pp132.