Architecture Considerations for Multi-Bit ΣΔ ADCs-Reference-Cited by-同舟云学术

Architecture Considerations for Multi-Bit ΣΔ ADCs

Published:2002 Issue: Volume: Page:135-159
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Container-title:Analog Circuit Design
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Author:

Brooks Todd

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/0-306-47951-6_7

Reference22 articles.

1. L. R. Carley, “A noise-shaping coder topology for 15+ bit converters,” IEEE JSSC, vol. SC-24, pp.267–273, April 1989.

2. J. W. Fattaruso, S. Kiriaki, M. de Wit, and G. Warwar, “Self-calibration techniques for a second order multibit sigma-delta modulator,” IEEE JSSC, Vol. 28, pp. 1216–1223, Dec. 1993.

3. R. T. Baird and T. S. Fiez, “A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multi-bit DAC,” IEEE JSSC, Vol. 31, pp. 312–320, Mar. 1996.

4. E. Fogleman, I. Galton, W. Huff, and H. Jensen, “A 3.3V single-poly CMOS Audio ADC Delta-Sigma Modulator with 98-dB Peak SINAD and 105dB Peak SFDR,” IEEE JSSC, Vol. 35, pp. 297–307, Mar. 2000.

5. Y. Geerts, M. S. Steyaert, and W. Sansen, “A high-performance multi-bit ΔΣ CMOS ADC,” IEEE JSSC, vol. 35, pp. 1829–1840, Dec. 2000.

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