Author:
Baños Raul,Gil Consolación,Ortega Julio,Montoya Francisco G.
Publisher
Springer Berlin Heidelberg
Reference19 articles.
1. Alpert, C.J., and Kahng, A., Recent Developments in Netlist Partitioning: A Survey. Integration: the VLSI Journal, 19/ 1–2 (1995) 1–81.
2. Banerjee, P.: Parallel Algorithms for VLSI Computer Aided Design. Prentice Hall, Englewoods Cliffs, NJ, 1994.
3. Gil, C.; Ortega, J., and Montoya, M.G., Parallel VLSI Test in a Shared Memory Multiprocessors. Concurrency: Practice and Experience, 12/5 (2000) 311–326.
4. Klenke, R.H., Williams, R.D., and Aylor, J.H., Parallel-Processing Techniques for Automatic Test Pattern Generation, IEEE Computer, (1992) 71–84.
5. Gil, C. and Ortega, J., A Parallel Test Pattern Generator based on Reed-Muller Spectrum, Euromicro Workshop on Parallel and Distributed Processing, IEEE (1997) 199–204.
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19 articles.
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