An Optimized S-Box Circuit Architecture for Low Power AES Design-Reference-Cited by-同舟云学术

An Optimized S-Box Circuit Architecture for Low Power AES Design

Published:2003 Issue: Volume: Page:172-186
ISSN:0302-9743
Container-title:Cryptographic Hardware and Embedded Systems - CHES 2002
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Author:

Morioka Sumio,Satoh Akashi

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-36400-5_14

Reference18 articles.

1. J. Daemen and V. Rijmen, “AES Proposal: Rijndael,” http://csrc.nist.gov/ encryption/aes/rijndael/Rijndael.pdf .

2. National Institute of Standards and Technology (NIST), “Advanced Encryption Standard (AES)”, FIPS Publication 197, http://csrc.nist.gov/encryption/ aes/index.html , Nov. 2001.

3. Lect Notes Comput Sci;H. Kuo,2001

4. B. Weeks et al., “Hardware Performance Simulation of Round 2 Advanced Encryption Standard Algorithm,” http://csrc.nist.gov/encryption/aes/round2/ NSA-AESfinalreport.pdf .

5. Lect Notes Comput Sci;M. McLoone,2001

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