Author:
Barik Rajkishore,Sarkar Vivek
Publisher
Springer Berlin Heidelberg
Reference21 articles.
1. Bitwise benchmarks, http://www.cag.lcs.mit.edu/bitwise/bitwise_benchmarks.htm
2. Gcc compiler (2004), http://gcc.gnu.org/
3. Berlin, D., Edelsohn, D., Pop, S.: High-level loop optimizations for gcc. In: The 2004 GCC Developers Summit (2004)
4. Briggs, P., Cooper, K.D., Torczon, L.: Improvements to graph coloring register allocation. ACM Transactions on Programming Languages and Systems 16(3), 428–455 (1994)
5. Brooks, D., Martonosi, M.: Dynamically exploiting narrow width operands to improve processor power and performance. In: HPCA 1999: Proceedings of the The Fifth International Symposium on High Performance Computer Architecture, p. 13. IEEE Computer Society, Los Alamitos (1999)
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