Power, Clock, and Global Signal Distribution

Author:

Zarkesh-Ha P.

Publisher

Springer US

Reference36 articles.

1. J.A. Davis and J.D. Meindl, “Compact distributed RLC models for multilevel interconnect networks,” IEEE Symposium on VLSI Technology, pp. 165–166, June 1999.

2. S. M. Kang, “Performance-driven Layout of CMOS VLSI Circuits,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 881–884, 1990.

3. D. Stroobandt, “A priori wire length estimation based on Rent’s rule,” First International Workshop on System-Level Interconnect Prediction, April 1999.

4. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, “On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent’s rule,” IEEE Custom Integrated Circuit Conference, pp. 93–96, May 1998.

5. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, “Prediction of interconnect fan-out distribution using Rent’s rule,” International Workshop on the System-Level Interconnect Prediction, pp. 107–112, April 2000.

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