1. M. Azimi, N. Cherukuri, D.N. Jayasimha, A. Kumar, P. Kundu, S. Park, I. Schoinas, A.S. Vaidya, Integration challenges and tradeoffs for tera-scale architectures. Intel Technol. J. 11(3), 173–184 (2007)
2. M. Azimi, D. Dai, A. Kumar, A. Mejia, D. Park, S. Saharoy, A.S. Vaidya, Flexible and adaptive on-chip interconnect for tera-scale architectures. Intel Technol. J. 13(4), 62–79 (2009)
3. M. Azimi, D. Dai, A. Kumar, A.S. Vaidya, On-chip interconnect trade-offs for tera-scale many-core processors, in Designing Network-on-Chip Architectures in the Nanoscale Era, ed. by J. Flich, D. Bertozzi (Chapman & Hall/CRC, Boca Raton, 2011)
4. R.V. Bopanna, S. Chalasani, Fault-tolerant wormhole routing algorithms for mesh networks. IEEE Trans. Comput. 44(7), 848–864 (1995)
5. G.M. Chiu, The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000)