Author:
Paul Somnath,Bhunia Swarup
Reference12 articles.
1. J. Maiz, S. Hareland, K. Zhang, P. Armstrong, “Characterization of Multi-bit Soft Error events in advanced SRAMs”, in Intl. Electron Devices Meeting, 2003
2. C.W. Slayman, “Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations”. IEEE Trans. Device Mater. Reliab. 5(3), 397–404 (2005)
3. K. Osada, K. Yamaguchi, Y. Saitoh, “SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect”. IEEE J. Solid State Circ. 39(5), 827–833 (2004)
4. D.M. Kwai et al., “Detection of SRAM Cell Stability by Lowering Array Supply Voltage”, in Asian Test Symposium, 2000
5. A. Pavlov et al., “Weak cell detection in deep-submicron SRAMs: A programmable detection technique”. IEEE J. Solid State Circ. 41(10), 2334–2343 (2006)