New DfM Domain: Stress Effects
Publisher
Springer New York
Reference68 articles.
1. Zhang, X.: Chip-package interaction and its impact on the reliability of flip-chip packages. Ph.D. Thesis, UT Austin (2009) 2. Sukharev, V., Zschech, E.: Stress management for 3D IC’s using through-silicon vias. AIP Conf. Proc. 1378, 21–49 (2011) 3. Radojcic, R., Novak, M., Nakamoto, M.: TechTuning: stress management for 3D through-silicon via stacking technologies. AIP Conf. Proc. 1378, 5–20 (2011) 4. Thompson, M.S.E., Armstrong, M., Auth, C., Cea, S., Chau, R., Glass, G., Hoffman, T., Klaus, J., Zhiyong, M., Mcintyre, B., Murthy, A., Obradovic, B., Shifren, L., Sivakumar, S., Tyagi, S., Ghani, T., Mistry, K., Bohr, M., El-Mansy, Y.: IEEE Electron. Devices. Lett. 25, 191–193 (2004) 5. Flachowsky, S., Wei, A., Illgen, R., Hermann, T., Hocnischel, J., Horstmann, M., Klix, W., Stenzel, R.: IEEE Trans. Electron. Devices 57, 1343–1354 (2010)
|
|