Author:
Buchwalter Stephen L.,Edwards Maurice E.,Gamota Daniel,Gaynes Michael A.,Tran Son K.
Reference141 articles.
1. N. G. Koopman, T. C. Reiley and P. A. Totta,“Chip-to-package Interconnections,” Microelectronics Packaging Handbook, R.R. Tummala and E. J. Rymaszewski, eds., New York: Van Nostrand Reinhold, 1989, pp. 361–453.
2. Proc. TMS Ann. Meeting;KJ Puttlitz,1997
3. K. Beckham, A. Kolman and K. Puttlitz, “Solder Interconnection Structure for Joining Semiconductor Devices to Substrates that have Improved Fatigue Life and Process for Making,” U.S. Patent 4, 604,644 (1986).
4. Proc. 40th IEEE Electr. Comp. Technol Conf;HM Tong,1990
5. H. M. Tong, L. S. Mok, K. R. Grebe, H. L. Yeh, K. K. Srivastava and J. T. Coffin, “Effects of Parylene Coating on the Thermal Fatigue Life of Solder Joints in Ceramic Packages,” IEEE Trans. Comp., Hybr. Manuf.TechnoL, 16 (5): pp. 571–575, 1993.
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