Logic Synthesis for Low Power-Reference-Cited by-同舟云学术

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Logic Synthesis for Low Power

Published:2002 Issue: Volume: Page:197-223
ISSN:
Container-title:Logic Synthesis and Verification
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Author:

Benini Luca,Micheli Giovanni

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-1-4615-0817-5_8

Reference58 articles.

1. M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, M. Papaefthymiou, “Precomputation-based sequential logic optimization for low power,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 2, No. 4, pp. 426–436, Dec. 1994.

2. R. Bahar, H. Cho, G. Hachtel, G. Hachtel, E. Macii, F. Somenzi, “Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, pp. 1105–1115, Oct. 1997.

3. I. Bahar, D. Lampe, E. Macii, “Power optimization of technology dependent circuits based on symbolic computation of logic implications,” ACM Transactions on Design Automation of Electronic Systems vol. 5, no. 3, pp. 267–293, July 2000.

4. L. Benini, G. De Micheli, “Automatic synthesis of low-power gated-clock finite-state machines,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 6, pp. 630–643, June 1996.

5. L. Benini, G. De Micheli, Dynamic power management: design techniques and CAD tools, Kluwer, 1998.

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