Adaptive Voltage Optimization Techniques: Low Voltage SRAM Operation
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Publisher
Springer New York
Link
http://link.springer.com/content/pdf/10.1007/978-1-4614-4039-0_3.pdf
Reference17 articles.
1. G. Chen et al., Crosshars SRAM—an adaptive memory for mitigating parametric failures. in Proceedings of IEEE European Solid State Circuits Conference (ESSCIRC), pp. 366–369 (2010)
2. Y. Fujimura et al., A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149um2 cell in 32 nm high-K metal-gate CMOS. in Proceedings of International Solid State Conference (ISSCC), pp. 348–350, Feb 2010
3. O. Hirabayashi et al., A process-variation-tolerant dual-power-supply SRAM with 0.179um2 Cell in 40nm CMOS using level-programmable wordline driver. in Proceedings of International Solid State Conference (ISSCC), pp. 458–459, Feb 2009
4. M. Khellah et al., Word line and bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65 nm CMOS designs. Symposium on VLSI circuits digest of technical papers, pp. 9–10 (2006)
5. K. Nii et al., A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. Symposium on VLSI circuits digest of technical papers, pp. 212–213 (2008)
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