Reference21 articles.
1. M. A. Annaratone, Digital CMOS Circuit Design, Springer Science+Business Media New York, Boston, 1986.
2. M.A. Bayoumi and N. Ling, “Testing of a NORA CMOS Serial-Parallel Multiplier,” IEEE J. Solid-State Circuits, vol. 24, No. 2, pp. 494–503, April, 1989.
3. V, Friedman and S. Liu, “Dynamic Logic CMOS Circuits,” IEEE J. Solid-State Circuits, vol. SC-19, No. 2, pp.263–266, April, 1984.
4. N.F. Goncalves and H.J. De Man, “NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures,” IEEE J. Solid-State Circuits, vol. SC-18, No. 3, pp. 261–266, June, 1983.
5. M. Hoffmann and A.R. Newton, “A domino CMOS logic synthesis system,” Proc. IEEE Int. Symp. on Circuits and Systems, pp. 411–414, 1985.
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