Low Cost Chipless RFID Systems

Author:

Preradovic Stevan,Karmakar Nemai Chandra

Publisher

Springer New York

Reference83 articles.

1. R. R. Fletcher, “Low-cost electromagnetic tagging: design and implementation”, PhD Thesis, September 2002. Available< http://www.media.mit.edu/physics/publications/theses/97.02.fletcher.pdf

2. D. A. Hodges, H. G. Jackson, “Analysis and design of digital integrated circuits – 2nd Edition”, McGraw-Hill, New York, USA, 1988.

3. J. R. Baker, H. W. Li, D. E. Boyce, “CMOS circuit design, layout and simulation”, IEEE Press, New York, USA, 1998.

4. S. Natarajan, “A 32nm logic technology featuring 2nd –generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm² SRAM cell size in a 291Mb Array”, IEEE International Electron Devices Meeting 2008 IEDM 2008, pp:1–3, San Francisco, USA, 15–17 Dec. 2008.

5. S. Harma, V. P. Plessky, C. S. Hartmann, W. Steichen, “SAW RFID tag with reduced size”, IEEE Ultrasonics Symposium 2006, pp:2389–2392, Vancouver, Canada, Oct. 2006.

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