VHDL Designer’s Reference

Author:

Bergé Jean-Michel,Fonkoua Alain,Maginot Serge,Rouillard Jacques

Publisher

Springer US

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Logic Synthesis;Wiley Encyclopedia of Computer Science and Engineering;2007-12-14

2. Virtual instrument system software architecture description language;Journal of Zhejiang University-SCIENCE A;2001-10

3. A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models;Field-Programmable Custom Computing Technology: Architectures, Tools, and Applications;2000

4. Discrete Approach to PWL Analog Modeling in VHDL Environment;Analog VHDL;1998

5. The Design Cube: A Model for VHDL Designflow Representation and Its Application;High-Level System Modeling;1996

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