Author:
Sutaria Ketul B.,Velamala Jyothi B.,Ramkumar Athul,Cao Yu
Reference54 articles.
1. C. Constantinescu, “Trends and challenges in vlsi circuit reliability,” IEEE Computer Society, pp. 14–19, 2003.
2. Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2010. (Available at http://public.itrs.net ).
3. D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” Journal of Applied Physics, vol. 94, no. 1, pp. 1-18, 2003.
4. K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” J. Applied Physics, vol. 48, no. 5, pp. 2004-2014, 1977.
5. K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, N. J. Rohrer, “High-performance CMOS variability in the 65-nm regime and beyond,” IBM Journal of Research and Development, vol. 50, no. 4/5, pp. 433-449, July 2006.
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