Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors

Author:

Loitz Sacha,Wedler Markus,Stoffel Dominik,Brehm Christian,Kunz Wolfgang,Wehn Norbert

Publisher

Springer New York

Reference16 articles.

1. Basu, P., Das, S., A. Banerjee, Dasgupta, P., Chakrabarti, P., Mohan, C., Fix, L., Armoni, R.: Design-intent coverage-a new paradigm for formal property verification. IEEE Transactions on Computer-Aided Design 25(10), 1922–1934 (2006)

2. Bormann, J.: Vollständige Verifikation. Dissertation, Technische Universität Kaiserslautern (2009)

3. Bormann, J., Beyer, S., Maggiore, A., Siegel, M., Skalberg, S., Blackmore, T., Bruno, F.: Complete formal verification of TriCore2 and other processors. In: DVCon (2007)

4. Bormann, J., Busch, H.: Verfahren zur Bestimmung der Güte einer Menge von Eigenschaften (Method for determining the quality of a set of properties). European Patent Application, Publication Number EP1764715 (2005)

5. Claessen, K.: A coverage analysis for safety property lists. In: Proc. International Conference on Formal Methods in Computer-Aided Design (FMCAD), pp. 139–145. IEEE Computer Society (2007). DOI  http://doi.ieeecomputersociety.org/10.1109/FAMCAD.2007.32

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