1. K. A. Sack, R. C. Lyman and G. T. Chang, Evolution of the concept of a computer on a slice, Proc. IEEE, vol. 52, pp. 1713–1770 (1964).
2. R. C. Aubusson and I. Catt, Wafer-scale integration — a fault-tolerant procedure, IEEE J. Solid-State Circuits, vol. SC-13, pp. 339–344 (1978).
3. A. J. Rushton and C. R. Jesshope, The reconfigurable processor array — an architecture in need of WSI, in Wafer Scale Integration, C. Jesshope and W. Moore (Eds), Adam Hilger, Bristol, England, pp. 148–158 (1986).
4. C. Jesshope and W. Moore (Eds), Wafer Scale Integration, Adam Hilger, Bristol, England (1986).
5. G. Saucier and J. Trihle (Eds), Wafer Scaie Integration, North-Holland, Amsterdam, The Netherlands (1986).