Spatial Data Locality with Respect to Degree of Parallelism in Processor-and-Memory Hierarchies

Author:

Figueiredo Renato J. O.,Fortes José A. B.,Miled Zina Ben

Publisher

Springer Berlin Heidelberg

Reference15 articles.

1. Cmelik, B., Keppel, D.: Shade: A fast instruction-set simulator for execution profiling. In: Proceedings of the 1994 SIGMETRICS Conf. on Measurement and Modeling of Computer Systems (1994)

2. Patterson, D., et al.: A Case for Intelligent RAM: IRAM. IEEE Micro, Los Alamitos (1997)

3. Figueiredo, R.J.O., Fortes, J.A.B., Ben-Miled, Z., Taylor, V., Eigenmann, R.: Impact of Computing-in-Memory on the Performance of Processorand- Memory Hierarchies. Technical Report TR-ECE-98-1, Electrical and Computer Engineering Department, Purdue University (1998)

4. Hagersten, E., Landin, A., Haridi, S.: DDM - A Cache-Only Memory Architecture. IEEE Computer, Los Alamitos (1992)

5. Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Francisco (1996)

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