1. Kindly confirm the inserted conference locations in the following references: [1, 3, 5, 15, 17, 19–21, 23, 25–26, 30, 32–33, 35–36]. P. Scholtens, D. Smola, M. Vertregt, Systematic power reduction and performance analysis of mismatch limited ADC designs, in Proceedings of ISPED, Bordeaux, Aug 2005, pp. 78–83
2. Kindly confirm the updated details in Murmann (2006) and Rabaey et al. (2003). B. Murmann, Limits on ADC power dissipation, in Analog Circuit Design, ed. by A.H.M. van Roermund, H. Casier, M. Steyaert (Springer, Dordrecht, 2006), pp. 351–367
3. Y. Chiu, B. Nikolic, P.R. Gray, Scaling of analog-to-digital converters into ultra-deep-submicron CMOS, in Proceedings of IEEE CICC, San Jose, 2005, pp. 375–382
4. Kindly confirm the updated journal title in the reference “Uyttenhove (2002)” and “Vertregt et al. (2003)”. K. Uyttenhove, M. Steyaert, Speed–power–accuracy tradeoff in high-speed CMOS ADCs. IEEE Trans. Circuits Syst. (CAS-II) 49(4), 280–287 (2002)
5. P. Kinget, M. Steyaert, Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits, in Proceedings of IEEE CICC, Rochester, 1988, pp. 333–336