A Perspective on Fast-SPICE Simulation Technology-Reference-Cited by-同舟云学术

A Perspective on Fast-SPICE Simulation Technology

Published:2011 Issue: Volume: Page:23-42
ISSN:
Container-title:Simulation and Verification of Electronic and Biological Systems
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Author:

Rewieński Michał

Publisher

Springer Netherlands

Link

http://link.springer.com/content/pdf/10.1007/978-94-007-0149-6_2.pdf

Reference16 articles.

1. Cadence White Paper (2004), Using Hierarchy and Isomorphism to Accelerate Circuit Simulation, available at http://w2.cadence.com/whitepapers/5084_AccelCircuitWP_FNL.pdf

2. Celik M, Pileggi L, Odabasioglu A (2002), IC Interconnect Analysis, Kluwer Academic Publishers, Boston

3. Kerns KJ, Bhattacharya M, Rudnaya S, Gullapalli K (2007), Automatic, Hierarchy-Independent Partitioning Method for Transistor-Level Circuit Simulation, patent application submitted to U.S. Patent and Trademark Office (pending)

4. Kerns KJ, Peng Z (2008), SPICE optimized for arrays, U.S. patent no. 7,324,363

5. Karypis G, Kumar V, hMETIS 1.5: A hypergraph partitioning package, Technical Report, Department of Computer Science, Univ. of Minnesota, available at http://www.cs.umn.edu/~metis

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