Wafer Topography Simulation
Publisher
Springer Netherlands
Reference67 articles.
1. W. G. Oldham, S. Nandgaonkar, A. R. Neureuther, and M. M. O’Toole, “A General Simulator for VLSI Lithography and Etching Processes: Part I — Application to Projection Lithography,” IEEE Trans. on Electron Devices, Vol. ED-26, No. 4, pp. 717–722 April 1979. 2. W. G. Oldham, A. R. Neureuther, C. Sung, J. L. Reynolds and S. N. Nandgaonkar, “A General Simulator for VLSI Lithography and Etching Processes: Part II-Application to Deposition and Etching,” IEEE Trans. on Electron Devices, Vol. ED-27, No. 8, pp. 1455–1459, August 1980. 3. A. R. Neureuther, “Simulating VLSI Wafer Topography,” 1980 IEDM Technical Digest, pp 214–218, (December). 4. R.W. Dutton and S.E. Hansen, “Process Modeling of Integrated Circuit Device Technology,” Proceedings of the IEEE, Vol. 69, No. 10, pp. 1305–1320, October 1981. 5. H. Ryssel, K. Haberger, K. Hoffmann, G. Prinke, R. Dumcke and A. Sachs, “Simulation of Doping Processes,” IEEE Trans on Electron Devices, Vol. ED-27, No. 8, pp. 1484–1492, August 1980.
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