1. Amdahl, G.M.: Validity of the single processor approach to achieving large-scale computing capabilities. AFIPS Conf. Proc. 30, 483–485 (1967)
2. Granado, J.M., et al.: IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration. Microelectron. J. 40(6), 1032–1040 (2009)
3. Granado-Criado, J.M., et al.: A new methodology to implement the AES algorithm using partial and dynamic reconfiguration, INTEGRATION. VLSI J. 43(1), 72–80 (2010)
4. Gonzalez, I., et al.: Using partial reconfiguration in cryptographic applications: an implementation of the IDEA algorithm, FPL 2003, LNCS 2778, pp. 194–203. Springer, Berlin (2003)
5. Alaoui Ismaili, Z.E.A., Moussa, A.: Self-partial and dynamic reconfiguration implementation for AES using FPGA, IJCSI Int. J. Comput. Sci. Issues. 2, 33–40 (2009)