An FPGA 2D-convolution unit based on the CAPH language

Author:

Aguilar-González AbielORCID,Arias-Estrada Miguel,Pérez-Patricio Madaín,Camas-Anzueto J. L.

Publisher

Springer Science and Business Media LLC

Subject

Information Systems

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Neural network accelerator with fast buffer design for computer vision;Journal of Real-Time Image Processing;2024-03-08

2. A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications;Circuits, Systems, and Signal Processing;2019-03-11

3. FPGA Design of Real-Time MDFD System Using High Level Synthesis;IEEE Access;2019

4. Towards Executing Computer Vision Functionality on Programmable Network Devices;Proceedings of the 1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms - ENCP '19;2019

5. Depth from a Motion Algorithm and a Hardware Architecture for Smart Cameras;Sensors;2018-12-23

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