A hardware-friendly logarithmic quantization method for CNNs and FPGA implementation-Reference-Cited by-同舟云学术

A hardware-friendly logarithmic quantization method for CNNs and FPGA implementation

Published:2024-06-06 Issue:4 Volume:21 Page:
ISSN:1861-8200
Container-title:Journal of Real-Time Image Processing
language:en
Short-container-title:J Real-Time Image Proc

Author:

Jiang Tao,Xing Ligang,Yu Jinming,Qian Junchao

Funder

National Natural Science Foundation of China

Natural Science Foundation of Shandong Province

Anhui Province Funds for Distinguished Young Scientists

Collaborative Innovation Program of Hefei Science Center, CAS

China Postdoctoral Science Foundation

Project of Postdoctoral Innovation of Shandong Province

Publisher

Springer Science and Business Media LLC

Link

https://link.springer.com/content/pdf/10.1007/s11554-024-01484-y.pdf

Reference31 articles.

1. Chai, J., Zeng, H., Li, A., Ngai, E.: Deep learning in computer vision: a critical review of emerging techniques and application scenarios. Mach. Learn. Appl. 6, 100134 (2021)

2. Zhou, Y., Yen, G.G., Yi, Z.: A knee-guided evolutionary algorithm for compressing deep neural networks. IEEE Trans. Cybern. 51, 1626–1638 (2021)

3. Rajpal, D., Garg, A.R.: Deep learning model for recognition of handwritten devanagari numerals with low computational complexity and space requirements. IEEE Access 11, 49530–49539 (2023)

4. Yu, C., et al.: S-densenet: a densenet compression model based on convolution grouping strategy using skyline method. IEEE Access 7, 183604–183613 (2019)

5. Lee, J., Kim, W., Kim, S., Kim, J.-H.: Post-quantum cryptography coprocessor for risc-v cpu core. 2022 International Conference on Electronics, Information, and Communication (ICEIC), Jeju, Korea, pp. 1–2 (2022)