FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT

Author:

Jana Jhilam,Chowdhury Ritesh Sur,Tripathi Sayan,Bhaumik Jaydeb

Publisher

Springer Science and Business Media LLC

Subject

Information Systems

Reference24 articles.

1. Acharya, T.: Intel Corp, Architecture for computing a two-dimensional discrete wavelet transform, U.S. Patent No. 6,178,269, (2001)

2. Kumar, M.N., Hemanth, J., Prasad, K.D.: VLSI Implementation of DWT Using Systolic Array Architecture. International Journal of Recent Technology and Engineering (IJRTE) 1, 67–73 (2012)

3. Meher, P.K., Mohanty, B.K., Patra, J.C.: Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform. IEEE Transactions on Circuits and Systems II: Express Briefs 55(2), 151–155 (2008)

4. Daubechies, I., Ten lectures on wavelets. Society for industrial and applied mathematics, (1992)

5. Jana, J., Tripathi, S., Chowdhury, R.S., Bhattacharya, A., Bhaumik, J.: Efficient, an area, architecture, V.L.S.I., for 1-D and 2-D discrete wavelet transform (DWT) and inverse discrete wavelet transform (IDWT). Dev. Integr. Circuit IEEE 2021, 378–382 (2021)

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