Author:
Klaiber Michael J.,Bailey Donald G.,Simon Sven
Funder
Deutsche Forschungsgemeinschaft
Publisher
Springer Science and Business Media LLC
Reference17 articles.
1. Xilinx Inc.: Xilinx User Guide—Virtex-6 FPGA Memory Resources UG363 (v1.6). Xilinx Inc., San Jose, CA, USA (2011)
2. Appiah, K., Hunter, A., Dickinson, P., Owens, J.: A run-length based connected component algorithm for FPGA implementation. In: International Conference on Field Programmable Technology, FPT 2008, pp. 177–184 (2008)
3. Bailey, D., Johnston, C.: Single pass connected components analysis. In: Proceedings of Image and Vision Computing New Zealand, pp. 282–287 (2007)
4. Bailey, D., Johnston, C., Ma, N.: Connected components analysis of streamed images. In: International Conference on Field Programmable Logic and Applications (FPL 2008), pp. 679–682 (2008)
5. Galler, B.A., Fisher, M.J.: An improved equivalence algorithm. Commun. ACM 7(5), 301–303 (1964)
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