Sub-Threshold Operation: Theory and Challenges
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-16136-5_2
Reference39 articles.
1. Bol D, Ambroise R, Flandre D, Legat JD (2008) Analysis and minimization of practical energy in 45nm subthreshold logic circuits. In: Proceedings of the IEEE international conference on computer design (ICCD), pp 294–300. DOI: 10.1109/ICCD.2008.4751876
2. Bol D, Ambroise R, Flandre D, Legat JD (2009) Interests and limitations of technology scaling for subthreshold logic. IEEE Trans Very Large Scale Integ (VLSI) Syst 17(10):1508–1519. DOI: 10.1109/TVLSI.2008.2005413
3. Bol D, Flandre D, Legat JD (2009) Technology flavor selection and adaptive techniques for timing-constrained 45 nm subthreshold circuits. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design (ISLPED), pp 21–26
4. Bol D, Hocquet C, Flandre D, Legat JD (2010) The detrimental impact of negative celsius temperature on ultra-low-voltage CMOS logic. In: Proceedings of the IEEE European solid-state circuits conference (ESSCIRC), pp 522–525. DOI: 10.1109/ESSCIRC.2010.5619758
5. Bol D, De Vos J, Hocquet C, Botman F, Durvaux F, Boyd S, Flandre D, Legat JD (2013) Sleepwalker: A 25-MHz 0.4-V sub-mm2 7-μW/MHz microcontroller in 65-nm LP/GP CMOS for low-carbon wireless sensor nodes. IEEE J Solid State Circuits 48(1):20–32. DOI: 10.1109/JSSC.2012.2218067
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