On the Mitigation of Cache Hostile Memory Access Patterns on Many-Core CPU Architectures-Reference-Cited by-同舟云学术

On the Mitigation of Cache Hostile Memory Access Patterns on Many-Core CPU Architectures

Published:2017 Issue: Volume: Page:348-362
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Deakin Tom,Gaudin Wayne,McIntosh-Smith Simon

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-67630-2_26

Reference10 articles.

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2. Deakin, T., McIntosh-Smith, S., Martineau, M., Gaudin, W.: An improved parallelism scheme for deterministic discrete ordinates transport. Int. J. High Perform. Comput. Appl. http://hpc.sagepub.com/cgi/doi/10.1177/1094342016668978

3. Lecture Notes in Computer Science;T Deakin,2016

4. Intel: Programming with Intel Streaming SIMD Extensions, Intel 64 and IA-32 Architectures Software Developer’s Manual, chap. 10, vol. 1. Intel Corporation, December 2016

5. Jeffers, J., Reinders, J., Sodani, A.: Trinity workloads. In: Intel Xeon Phi Processor High Performance Programming, chap. 25, pp. 549–579. Morgan Kaufmann, Boston (2016). http://www.sciencedirect.com/science/article/pii/B9780128091944000259

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