Author:
Dghais Wael,Chen Yuanfang
Publisher
Springer International Publishing
Reference16 articles.
1. Dghais, W., Cunha, T. R., & Pedro, J. C. (2013, October). A novel two-port behavioral model for I/O buffer overclocking simulation. IEEE Transactions on Components, Packaging and Manufacturing Technology, 3(10), 1754–1763.
2. Nadezhin, D., Gavrilov, S., Glebov, A., Egorov, Y., Zolotov, V., & Blaauw, D (2003, November). SOI transistor model for fast transient simulation, In Proceedings of the IEEE/ACM international conference on Computer-aided design (pp. 120–128).
3. Dghais, W., & Rodriguez, J. (2015, March). Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation. In IEEE conference Design Automation and Test in Europe, Grenoble, France.
4. Rossi, D., Steiner, C., & Metra, C. (2006). Analysis of the impact of bus implemented EDCs on on-chip SSN (pp. 59–64). Europe: Design Automation and Test.
5. Dghais, W., & Rodriguez, J. (2015, May). IBIS model formulation and extraction for SPI evaluation. In IEEE workshop on signal and power integrity (SPI), Berlin, Germany.