Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach-Reference-Cited by-同舟云学术

Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach

Published:2017 Issue: Volume: Page:93-105
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Bollengier Théotime,Lagadec Loïc,Najem Mohamad,Le Lann Jean-Christophe,Guilloux Pierre

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-56258-2_9

Reference17 articles.

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2. Nanoxplore. http://www.nanoxplore.com

3. ADICSYS - eFPGA (embedded FPGA) IP. http://www.adicsys.com

4. Abramovici, M., Bradley, P., Dwarakanath, K.N., Levin, P., Memmi, G., Miller, D.: In: Sentovich, E. (ed.) Proceedings of DAC 2006, pp. 7–12. ACM (2006)

5. Wilton, S.J., Kafafi, N., Wu, J.C., Bozman, K.A., Aken’Ova, V.O., Saleh, R.: Design considerations for soft embedded programmable logic cores. IEEE J. Solid-State Circ. 40(2), 485–497 (2005)

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