LP-P $$^2$$ IP: A Low-Power Version of P $$^2$$ IP Architecture Using Partial Reconfiguration
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-56258-2_2
Reference19 articles.
1. Cardona, L.A., Ferrer, C.: AC_ICAP: a flexible high speed ICAP controller. Int. J. Reconfigurable Comput. (2015). doi: 10.1155/2015/314358
2. Possa, P.R., Mahmoudi, S.A., Harb, N., Valderrama, C., Manneback, P.: A multi-resolution FPGA-based architecture for real-time edge and corner detection. IEEE Trans. Comput. 63, 2376–2388 (2014). doi: 10.1109/TC.2013.130
3. Possa, P., Harb, N., Dokládalová, E., Valderrama, C.: P $$^2$$ IP: a novel low-latency programmable pipeline image processor. Microprocess. Microsyst. 39, 529–540 (2015). doi: 10.1016/j.micpro.2015.06.010
4. da Cunha Possa, P.R.: Reconfigurable low-latency architecture for real-time image and video processing. UMONS (2013)
5. Liu, S., Pittman, R.N., Forin, A.: Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller. In: Microsoft Research (2009)
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