Author:
Haimoto Takashi,Yamamoto Eiichi,Mitsui Takahiko,Ito Toshihiro,Yoshida Tsuyoshi,Bandoh Tsubasa,Saito Kazuta,Yamamoto Masahiro
Publisher
Springer International Publishing
Reference18 articles.
1. Kim YS (2013) Advanced wafer thinning technology and feasibility test for 3D integration. Microelectron Eng 107:65–71
2. Hattori T, Osaka T, Okamoto A, Saga K, Kuniyasu H (1998) Contamination removal by single wafer spin cleaning with repetitive use of ozonized water and dilute HF. J Electrochem Soc 145:3278–3284
3. Sun WP (2004) Fine grinding of silicon wafers: a mathematical model for the wafer shape. Int J Mach Tool Manuf 44:707–716
4. Kim YS, Kodama S, Mizushima Y, Maeda N, Kitada H, Fujimoto K, Nakamura T, Suzuki D, Kawai A, Arai K, Ohba T (2014) Ultra thinning down to 4-μm using 300-mm wafer proven by 40-nm node 2 Gb DRAM for 3D multiStack WOW applications. Symposia on VLSI Technology. Dig 26–27
5. Koyanagi M, Nakagawa Y, Lee KW, Nakamura T, Yamada Y, Inamura K, Park KT, Kurino H (2001) Neuromorphic vision chip fabricated using three-dimensional integration technology. ISSCC digital technical papers, pp 270–271