Trends in 3D Integrated Circuit (3D-IC) Testing Technology
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-18675-7_8
Reference61 articles.
1. Noia B, Chakrabarty K (2013) Pre-bond probing of through-silicon vias in 3-D stacked ICs. IEEE Trans Comput Aided Des Integr Circuits Syst 32(4):547–558
2. Noia B, Panth S, Chakrabarty K, Lim SK (2012) Scan test of die logic in 3D ICs using TSV probing. In: Proceedings of IEEE international test conference (ITC), pp 1–8
3. Chen PY, Wu CW, Kwai DM (2010) On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. In: Proceedings of IEEE VLSI test symposium (VTS), pp 263–268
4. Cho MK, Liu C, Kim DH, Lim SK, Mukhopadhyay S (2010) Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. In: Proceedings of IEEE/ACM international conference on computer-aided design (ICCAD), pp 694–697
5. Cho MK, Liu C, Kim DH, Lim SK, Mukhopadhyay S (2011) Pre-bond and post-bond test and signal recovery structure to characterize and repair TSV defect induced signal degradation in 3-D system. IEEE Trans Compon Packag Manuf Technol 1(11):1718–1727
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