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Logic Encryption

Published:2017 Issue: Volume: Page:71-88
ISSN:
Container-title:Hardware Protection through Obfuscation
language:
Short-container-title:

Author:

Rajendran Jeyavijayan,Garg Siddharth

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-49019-9_3

Reference32 articles.

1. Roy J, Koushanfar F, Markov IL (2008) EPIC: ending piracy of integrated circuits. In: Proceedings of the IEEE/ACM design, automation and test in Europe, pp 1069–1074

2. Chakraborty RS, Bhunia S (2009) HARPOON: an obfuscation-based SoC design methodology for hardware protection. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(10):1493–1502

3. Plaza SM, Markov IL (2015) Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Trans Comput-Aided Des Integr Circuits Syst 34(6):961–971

4. Rajendran J, Zhang H, Zhang C, Rose G, Pino Y, Sinanoglu O, Karri R (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64(2):410–424

5. Rajendran J, Pino Y, Sinanoglu O, Karri R (2012) Logic encryption: a fault analysis perspective. In: Proceedings of the IEEE/ACM design, automation and test in Europe, pp 953–958

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2020-05-01

2. Enhancements to SAT Attack;ACM Transactions on Design Automation of Electronic Systems;2018-07-31

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