Publisher
Springer International Publishing
Reference50 articles.
1. Dennard R, Gaensslen F, Rideout V, Bassous E, LeBlanc A (1974) Design of ion-implanted MOSFETs with very small dimensions. IEEE J Solid-State Circuits 9:256–268
2. Buchanan D (1999) Scaling the gate dielectric: materials, integration and reliability. IBM J Res Dev 43:245–264
3. Yeo Y, Lu Q, Lee W, King T-J, Hu C, Wang X, Ma T (2000) Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric. IEEE Electron Device Lett 21:540–542
4. Bai P et al (2004) A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-κ ILD and 0.57 mm2 SRAM cell. In: IEDM Technical Digest, pp 657–660
5. Antoniadis D, Aberg I, Ni Chleirigh C, Nayfeh O, Khakifirooz A, Hoyt J (2006) Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations. IBM J Res Dev 50:363–376
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献