Low-Power Design of Hybrid Instruction Cache Based on Branch Prediction and Drowsy Cache
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-00536-2_40
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5. Zhang C, Zhou HW et al. (2006) Architectural leakage power reduction method for instruction cache in ultra deep submicron microprocessors. In: The 11th Asia-Pacific computer systems architecture conference. Springer, Heidelberg, 588–594. doi: 10.1007/11859802_62
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