Validation of Railway Interlocking Systems by Formal Verification, A Case Study

Author:

Bonacchi Andrea,Fantechi Alessandro,Bacherini Stefano,Tempestini Matteo,Cipriani Leonardo

Publisher

Springer International Publishing

Reference26 articles.

1. European Committee for Electrotechnical Standardization, CENELEC EN50128, Railway applications-Communication signalling and processing system software for railway control and protection systems

2. Simulink $$^{\textregistered }$$ ® : Design Verifier R2012b. MathWorks (2012)

3. Simulink $$^{\textregistered }$$ ® : User Guide R2012b. MathWorks (2012)

4. Bernardeschi, C., Fantechi, A., Gnesi, S., Larosa, S., Mongardi, G., Romano, D.: A formal verification environment for railway signaling system design. Formal Methods Syst. Des. 12, 139–161 (1998)

5. LNCS;A Biere,1999

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