1. J. Kumar, M.B. Tahoori, in Use of Pass-Transistor Logic to Minimize the Impact of Soft Errors in Combinational Circuits. Workshop on SELSE (2005), pp. 67–74
2. Q. Zhou, M.R. Choudhury, K. Mohanram, in Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. Proceedings of the European Test Symposium, Verbania (2008), pp. 179–184
3. S. Sayil, A.H. Shah, M.A. Zaman, M.A. Islam, Soft error mitigation using transmission gate with varying gate and body bias. IEEE Des. Test 99, 1(2015)
4. W. Zhao, Y. Cao, New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans. Electron Devices 53(11), 2816–2823 (2006)
5. T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd edn. (Wiley, 2011)