A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA

Author:

Palchaudhuri Ayan,Chakraborty Rajat Subhra

Publisher

Springer International Publishing

Reference33 articles.

1. Preu $$\beta $$ β er, T.B., Zabel, M., Spallek, R.G.: Accelerating computations on FPGA carry chains by operand compaction. In: 20th IEEE Symposium on Computer Arithmetic (ARITH), pp. 95–102 (2011)

2. Preu $$\beta $$ β er, T.B., Spallek, R.G.: Mapping basic prefix computations to fast carry-chain structures. In: International Conference on Field Programmable Logic and Applications (FPL), pp. 604–608 (2009)

3. Ahmed, T., Kundarewich, P.D., Anderson, J.H.: Packing techniques for Virtex-5 FPGAs. ACM Trans. Reconfig. Technol. Syst. (TRETS), 2(18), 18:1–18:24 (2009)

4. Xilinx Inc., Virtex-5 Libraries Guide for HDL Designs, UG621 (v 11.3) (2009). Cited 16 September 2009, http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/Virtex5_hdl.pdf

5. Ehliar, A.: Optimizing Xilinx designs through primitive instantiation. In: Proceedings of the 7th FPGAworld Conference, pp. 20–27 (2010)

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