1. IEEE Std. 1500: IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits. IEEE Press, New York, 2005.
2. E.J. Marinissen, J. Verbree, and M. Konijnenburg, “A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs”, VLSI Test Symposium, 2010.
3. K. Puttaswamy and G. H. Loh, “The Impact of 3-Dimensional Integration on the Design of Arithmetic Units,” in IEEE International Symposium on Circuits and Systems, 2006.
4. K. Puttaswamy and G. H. Loh, “Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors,” IEEE High Performance Computer Architecture, pp. 193–204, 2007.
5. 45nm PTM LP Model.
http://ptm.asu.edu/modelcard/LP/45nm_LP.pm
Accessed January 2011.