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Springer International Publishing
Reference152 articles.
1. B.J. Ahn, J.H. Sone, J.W. Kim, I.H. Choi, D.M. Kim, A simple and efficient self-limiting erase scheme for high performance split-gate flash memory cells. IEEE Electron Device Lett. 19, 438–440 (1998)
2. I. Arsovski, T. Hebig, D. Dobson et al., A 32 nm 0.58-fJ/bit/search 1-GHz ternary content addressable memory compiler using silicon-aware early-predict late-correct sensing with embedded deep-trench capacitor noise mitigation. IEEE J. Solid State Circuits 48(4), 932–939 (2013)
3. S. Atsumi, M. Kuriyama, A. Umezawa et al., A 16-Mb Flash EEPROM with a new self-data-refresh scheme for a sector erase operation. IEEE J. Solid State Circuits 29(4), 461–468 (1994)
4. N. Banno, M. Tada, T. Sakamoto, et al., A fast and low-voltage Cu complementary-atom- switch 1 Mb array with high-temperature retention, IEEE Symposium on VLSI Technology (VLSIT) Dig. Tech. Papers (2014), pp. 1–2
5. M. Bauer, R. Alexis, G. Atwood, et al., A multilevel-cell 32 Mb flash memory, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, 15–17 Feb. 1995 (1995), pp.132–133
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