Author:
Muller Jean-Michel,Brunie Nicolas,de Dinechin Florent,Jeannerod Claude-Pierre,Joldes Mioara,Lefèvre Vincent,Melquiond Guillaume,Revol Nathalie,Torres Serge
Publisher
Springer International Publishing
Reference23 articles.
1. R. C. Agarwal, F. G. Gustavson, and M. S. Schmookler. Series approximation methods for divide and square root in the Power3TM processor. In 14th IEEE Symposium on Computer Arithmetic (ARITH-14), pages 116–123, April 1999.
2. C. Anderson, N. Astafiev, and S. Story. Accurate math functions on the Intel IA-32 architecture: A performance-driven design. In Real Numbers and Computers, pages 93–105, July 2006.
3. C. Bruel. If-conversion SSA framework for partially predicated VLIW architectures. In 4th Workshop on Optimizations for DSP and Embedded Systems (ODES), New York, NY, USA, March 2006.
4. M. Cornea, C. Anderson, J. Harrison, P. T. P. Tang, E. Schneider, and C. Tsen. A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. In 18th IEEE Symposium on Computer Arithmetic (ARITH-18), pages 29–37, June 2007.
5. M. Cornea, J. Harrison, C. Anderson, P. T. P. Tang, E. Schneider, and E. Gvozdev. A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. IEEE Transactions on Computers, 58(2):148–162, 2009.