1. S. Ben-Yaakov, On the influence of switch resistances on switched-capacitor converter losses. IEEE Trans. Ind. Electron. 59(1), 638–640 (2012)
2. H. Bergveld, K. Nowak, R. Karadi, S. Iochem, J. Ferreira, S. Ledain, E. Pieraerts, M. Pommier, A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration, in IEEE Energy Conversion Congress and Exposition, 2009 (ECCE 2009) (2009), pp. 3698–3705
3. L. Chang, R.K. Montoye, B.L. Ji, A.J. Weger, K.G. Stawiasz, R.H. Dennard, A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2, in Proceedings of Symposium on VLSI Circuits (2010), pp. 55–56
4. J.F. Dickson, On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique. IEEE J. Solid State Circuits 11(3), 374–378 (1976)
5. R. Ghaida, G. Torres, P. Gupta, Single-mask double-patterning lithography for reduced cost and improved overlay control. IEEE Trans. Semicond. Manuf. 24(1), 93–103 (2011)