HLS-Based FPGA Acceleration of Building-Cube Stencil Computation
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-61566-0_42
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1. HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator;2024 IEEE International Conference on Consumer Electronics (ICCE);2024-01-06
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