Towards Drain Extended FinFETs for SoC Applications
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-02021-1_10
Reference24 articles.
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3. Jan, C.-H., Agostinelli, M., Buehler, M., Chen, Z.-P., Choi, S.-J., Curello, G., Deshpande, H., Gannavaram, S., Hafez, W., Jalan, U., Kang, M., Kolar, P., Komeyli, K., Lake, A., Lazo, N., Lee, S.-H., Leo, T., Lin, J., Lindert, N., Ma, S., McGill, L., Meining, C., Paliwal, A., Park, J., Phoa, K., Post, I., Pradhan, N., Prince, M., Rahman, A., Rizk, J., Rockford, L., Sacks, G., Tashiro, H., Tsai, C., Vandervoorn, P., Xu, J., Yang, L., Yeh, J.-Y., Yip, J., Zhang, K., Bai, P.: A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications. In: International electron devices meeting, pp. 647–650, Dec 2009
4. International Technology Roadmap for Semiconductors (ITRS) (2009)
5. Shrivastava, M., et al.: Toward system on chip (SoC) development using FinFET technology: challenges, solutions, process co-development & optimization guidelines. IEEE Trans. Electron Dev. 58(6), 1597–1607 (2011)
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